Field of the Invention
The present invention relates to a method for producing a semiconductor component with an encapsulated chip on a substrate. Such semiconductor components may be constructed, for example, as BGA (Ball Grid Array) components, PGA (Pin Grid Array) components, CSP (Chip Scale Packaging) components or the like. An alternative construction is described in an article entitled “Kraftpaket”, in Elekronikpraxis No. 21, Nov. 4, 1998, pages 60 to 63, wherein a PSGA (Polymer Stud Grid Array) component is presented in which a semiconductor chip is disposed on a polymer plastic substrate. That substrate can be produced in a precision injection-molding process. A conductive connection to a printed circuit board is produced by integrally formed pins (studs).
FIG. 1 diagrammatically illustrates a semiconductor component according to one of the types described above, in which a semiconductor chip enclosed by an encapsulation 6 is disposed on a substrate 1. The encapsulation can be produced by customary methods such as molding, gobe top methods, or the like. Interconnects 5 lead from the encapsulation 6 on the surface of the substrate. The interconnects are in turn conductively connected to elevations 11 on the underside of the substrate 1. The elevations 11 serve to make contact with a printed circuit board. The interconnects 5 on the top side of the substrate 1 are generally produced by coating the substrate with a metalization layer and subsequently structuring or patterning the metalization. The interconnects thus form elevated structures on the substrate, as is illustrated in an enlarged view in FIG. 2.
It is problematic in such a case that interspaces between the interconnects are inadequately sealed during molding encapsulation of the semiconductor chip in order to form the encapsulation. That sealing is necessary for the following reason: A tool used to effect molding encapsulation, with a cavity that it contains in order to accommodate a molding compound, must bear on the substrate surface in a planar manner and a contact pressure with which the tool is pressed onto the substrate surface must be able to seal the cavity, in order to ensure that no molding compound can escape from the cavity at a customary molding-encapsulation pressure of from 60 to 100 bar. Those regions at which an uneven substrate surface is present are then problematic. The consequence thereof, as is shown in FIG. 2, is that part of the molding compound escapes from the encapsulation region between the interconnects and leads to contamination of the substrate surface. In the extreme case, that can even make it impossible to encapsulate the component by molding. To date, the customary procedure for sealing those openings has been to provide a solder resist on the substrate 1 and thus between the interconnects as well. However, that requires an additional work step, as a result of which the method for producing the semiconductor component is prolonged and made more expensive.